خطا در برنامه FPGA. اشکال از کجاست؟

[solaleee]

سلام برنامه رو براتون گذاشتم میشه کمکم کنید تا خطاش رو حذف کنید
module f_c1(clk1,clk2,clk_sys,reset,clk_generate);
input clk1,clk2,clk_sys,reset;
output clk_generate ;
reg [100:0]count,count_1,next_state,state,next_state_1,state_ 1,clk_prd_1,clk_prd_2;
reg [100:0]clk_prd_total,clk_generate_count;
reg clk_generate;
parameter [3:0] s0=1,s1=2,counter=3,exit=4;
parameter [3:0] s00=5,ss=6,counter1=7,exit1=8;
reg rst;
reg rst_1;
reg clk_generate_en;
//-----------------------------------------
reg [2:0] shReg,shReg_1;
wire clkPos,clkPos_1;
always @(posedge clk_sys)
shReg = {shReg[1:0],clk1};
assign clkPos = ~shReg[1] & shReg[0];
always @(posedge clk_sys)
shReg_1 = {shReg_1[1:0],clk2};
assign clkPos_1 = ~shReg_1[1] & shReg_1[0];
//-----------------------------------------
always @(posedge clk_sys)
begin
if (reset==1'b1)
begin
rst=1'b1;
state = s0;next_state = s0 ;
end
else
begin
state = next_state;rst=rst;
end

case(state)
s0 :
begin

count = 0;
next_state = s1 ;
end

s1 :
begin
if (clkPos==1'b1)
begin
next_state = counter;
end
else next_state = s1 ;
end
counter :
begin
count = count + 1;
if (clkPos==1'b1)
next_state = exit;
else
next_state = counter;
end
exit :
begin
clk_prd_1 = count*2;
rst = 1'b1;
end
endcase
end
always @(posedge clk_sys)
begin
if (reset==1'b1)
begin
rst_1=1'b1;
state_1 = s00;next_state_1 = s00 ;
end
else
begin
state_1 = next_state_1;rst=rst;
end
case(state_1)
s00 :
begin
count_1 = 0;
next_state_1 = ss ;

end
ss :
begin
if (clkPos_1==1'b1)
begin
next_state_1 = counter1;
end
else next_state_1 = ss ;
end
counter1 :
begin
count_1 = count_1 + 1;
if (clkPos_1==1'b1)
next_state_1 = exit1;
else
next_state_1 = counter1;
end
exit1 :
begin
clk_prd_2 = count_1 * 2;
rst_1=1'b1;
end
endcase
clk_prd_total=(clk_prd_1*clk_prd_2)/(clk_prd_1+clk_prd_2);
end

always @(posedge clk_sys)
begin
if (reset==1)
begin
clk_generate_count = 0 ;
clk_generate_en = 1'b0 ;
end
else if (clk_prd_total != 0)
begin
if (clk_generate_count != clk_prd_total)
clk_generate_count = clk_generate_count + 1 ;
else
begin
clk_generate_en <= 1'b1 ;
clk_generate_count = 1'b0 ;
end

clk_generate_en = 0 ;
end

assign clk_generate = clk_generate_en;
end
endmodule
//--------------------------test_bench------------------------------------
module f_c1_tb ;
parameter counter = 3 ;
parameter s1 = 2 ;
parameter counter1 = 7 ;
parameter ss = 6 ;
parameter exit = 4 ;
parameter exit1 = 8 ;
parameter s00 = 5 ;
parameter s0 = 1 ;
reg clk_sys ;
reg clk2 ;
wire clk_generate ;
reg reset ;
reg clk1 ;
f_c1 #( counter , s1 , counter1 , ss , exit , exit1 , s00 , s0 )
DUT (
.clk_sys (clk_sys ) ,
.clk2 (clk2 ) ,
.clk_generate (clk_generate ) ,
.reset (reset ),
.clk1 (clk1 ));

initial begin clk1=1'b1;clk2=1'b1;clk_sys = 1'b1;end
always
begin
clk1 =! clk1;
#500000;
end
always
begin
clk2 =! clk2;
#1000000; //100k hz => 10 us one clk
end
always
begin
clk_sys =! clk_sys;
#10000; //50M hz => 20 ns
end
initial
begin
reset = 1'b1;
#20000;
reset = 1'b0;

end
endmodule

می خوام دو فرکانس ورودی رو با هم جمع کنه.